module top(input clk,input rst_n);

    wire   [2:0]  data_addr;
    wire   data_write_en;   
    wire   data_read_en;
    wire   [127:0]  data_write_data;

    // SOC_top Outputs
    wire  [127:0]  data_read_data;

    check u0 (
		.source ({data_addr,data_write_en,data_read_en,data_write_data}), // sources.source
		.probe  (data_read_data)   //  probes.probe
	);


    SOC_top  u_SOC_top (
        .clk                     ( clk               ),
        .rst_n                   ( rst_n             ),
        .data_addr               ( data_addr         ),
        .data_write_en           ( data_write_en     ),
        .data_read_en            ( data_read_en      ),
        .data_write_data         ( data_write_data   ),

        .data_read_data          ( data_read_data    )
    );
endmodule